As well known in the art, a semiconductor random access read/write memory device largely consists of a memory cell array composed of a number of memory cells arranged in rows and column in the form of a matrix, cell selector means to select at least one of the memory cells in response to supplied row and column address signals, means by which data is to be written into the selected memory cell, and means by which the data thus written into the selected cell is to be read from the memory cell. In a read/write memory of this type, two or more data lines are provided commonly for a single data input or output terminal and the cell selector means selects one of the rows of the memory array in response to the supplied row address signal. The cell selector means is further responsive to a portion of the supplied column address signal to specify two or more memory cells which are associated with particular two or more of the data lines and which have been selected in response to the row address signal. In response to the remaining portion of the column address signal, the selector means selects one of the selected two or more data lines so that only one memory cell is finally selected which is associated with both the selected data line and the selected row line. Data is written into or read out of the single particular memory cell through the data line with which the memory cell is associated.
In the meantime, a semiconductor read/write memory device of any type must be tested to see whether or not the individual memory cells and the various peripheral circuits of the device operate properly. For this purpose, test data is written into each of all the memory cells provided in the device and thereafter the data thus written into the individual memory cells is read out from every memory cell for comparison with the original data to see if the data read out from each memory cell is correctly in agreement with the original data. Major requirements of such a testing scheme include reduction of the period of time necessitated for the testing and the flexibility in nature of the data which can be used for testing purposes. For the testing of a memory device in which two or more memory cells are to be selected all at a time in response to row and column address signals, a testing circuit is used which is provided with a test data input circuit from which test data is to be supplied to each of the two or more data lines and is written concurrently into both or all of the selected memory cells connected to the data lines. This type of memory testing circuit contributes at least to significantly reducing the period of time required to carry out the test because of the fact that test data is written all at a time into a number of memory cells which are selected collectively.
A prior-art memory testing circuit of the type described however has an important drawback which stems from the fact that the two or more memory cells into which data is to be written for testing purposes receive only one and the same data from the testing circuit. The same data being used for both or all of the memory cells which are located adjacent each other, an interference test could not be conducted for those memory cells located adjacent each other. As well known in the art, this interference test is performed to see if the data stored in at least one of adjacent two memory cells might have been destroyed due to the capacitive coupling which might have been induced between the cells.
It is, accordingly, an important object of the present invention to provide a memory testing circuit useful for testing a semiconductor random access memory device in a significantly reduced period of time and with use of any desired kind of test data.
It is another important object of the present invention to provide an improved memory testing circuit capable of testing a semiconductor random access memory device in respect of an interference effect between adjacent memory cells of the device while offering significant reduction in the period of time required for the testing of the device.
Yet, it is another important object of the present invention to provide a semiconductor random access memory device incorporating an improved built-in memory testing circuit capable of performing an interference test for the memory cell array of the device.